1. Field of the Invention
The present invention relates to a semiconductor device which is directed to a reduced junction leakage failure caused by a residual refractory metal.
2. Description of the Prior Art
FIG. 6 is a sectional view taken in a direction of longitudinally of a resistor in a conventional semiconductor device. FIG. 7 is a plan view showing the separated state of the diffused resistor shown in FIG. 6. FIG. 8 is a sectional view taken in an orthogonal direction to the direction of longitudinally of the diffused resistor shown in FIG. 6. FIG. 9 is a plan view of the diffusion resistor shown in FIG. 8.
Referring to the figures, a non-silicide area 2 is deposited on a substrate (n-well) 1 of a semiconductor device, and the non-silicide area 2 forms a diffused resistor portion (resistive element) on both ends of which silicide areas 3 are deposited as terminals on which contact holes for conduction with an upper wiring are formed.
Accordingly, the non-silicide area 2 constitutes one resistor 4 having silicide areas 3 as two terminals on both ends thereof. Herein, since for instance, an A/D converter, a D/A converter and so on require a plurality of resistors 4 according to the number of gradation sequence thereof and the circuit composition thereof as shown in FIG. 7, these resistors 4 are uniformly provided in a parallel arrangement, to thereby improve the circuit accuracy. By the way, in recent portable devices, there has been a trend in which the resistor 4 is configured to have a length of 100 microns or more in order to obtain a large resistance value.
An isolation dielectric 5 (isolation oxide) is deposited on both the ends of the non-silicide area 2 on the substrate 1, and separates the resistor 2. A protective oxide 6 (SiO2) is deposited over the surface of the non-silicide area 2. The protective oxide 6 is formed by separating the non-silicide area 2 to become a diffused resistor portion on the substrate 1 and silicide areas 3 on both the ends of the non-silicide area 2, thereby preventing the silicide-formation reaction of the non-silicide area 2 to be expected as a diffused resistor portion on the substrate 1.
Herein, the method of separating and forming the non-silicide area 2 and silicide area 3 will be described. First of all, after depositing the protective oxide 6 all over the surface of the non-silicide area 2 except a wiring-connecting portion 2a (Refer to FIG. 9) on both the end portions thereof, a cobalt layer 7 is deposited all over the surface of the protective oxide 6 which spans the surfaces of the wiring—connecting portion 2a and the isolation dielectric 5, followed by annealing as they are. During annealing, Co chemically reacts with Si, to thereby form the silicide area 3 on the wiring-connecting portion 2a. On the other hand, unreacted Co remains on the surfaces of the protective oxide 6 and the isolation dielectric 5. Then, selectively removing the unreacted Co by use of an acid-mixture (H3PO4/CH3COOH/HNO3) and hydrogen peroxide (H2O2) produces the silicide area (CoSi2) 3 only within the wiring—connecting portions 2a. 
Referring to FIG. 8, a residual Co 7a (residual refractory metal) remains after removing the unreacted Co, and is observed by means of measurement by the total reflection fluorescent X-ray and the like, the residual quantity being very small (about 5E12–1E10 atom/cm2). This residual Co 7a diffuses into the inside of the substrate 1 by annealing afterwards. However, that Co is usually trapped within a micro defect layer existing in the boundary between the silicide layer of CoSiO2 and Si, and at a gettering site provided in the inside of the substrate 1.
In addition, referring to FIG. 6, contact holes 9 are provided on the side of both the ends of a contact interlayer dielectric 8, and corresponds to the silicide areas 3; upper aluminum wirings 10 are connected to the silicide areas 3 through the contact holes 9.
Since the conventional semiconductor device is configured as mentioned above, there has been the following drawback therein. That is, in a high-tech process where a microfabrication technique has been advanced, temperature-lowering and time-shortening of S/D annealing have been developed, and there might exist a microdefect caused by ion implantation damages within a normal junction. The microdefect existing within the junction presents no problem in electrical characteristics. However, when the residual Co 7a remaining on the protective oxide 6 and isolation dielectric 5 is trapped in the microdefect, that Co causes a silicide reaction. Thereby, the microdefect not only expands by the volume expansion thereof, but also the expanded microdefect grows up with an accelerating speed by the silicide reaction, when a new residual Co is trapped in the expanded microdefect. Before long, the expanded defect becomes a huge defect portion spanning the junction, and results in junction leakage in electrical characteristics. In other words, there has been a drawback that the residual refractory metal becomes a critical defect for the device. Particularly, the product equipped with a highly accurate A/D and D/A converter uses a lot of diffused resistors. When the semiconductor device requires a layout in which the active zone to be non-silicide is enlarged, there has been a problem that the residual Co easily combines with the microdefect of non-silicide area 2, rendering a factor of reduced yield.